1. Technical Field
The present invention relates to the conversion of serial data streams to multi-bit parallel data streams and, more particularly, to a modified-tree data deserializer.
2. Description of the Related Art
In electronic systems and circuits, when data is transferred from one system to another, the source system and destination system may process data at different rates. In such a case, it may be beneficial to convert between serial data at a high data rate to parallel data that is processed at a lower rate.
When selecting a data deserializer, speed, latency, power, and chip area are all metrics of the utility of that component. In modern high-speed systems, for example, a data deserializer may need to work at data rates in the tens of gigabytes per second. When data is transferred from the input of the deserializer to the output, a certain time delay is introduced called the latency. Different applications will have different latency needs, and high-performance computing systems may need a very low latency. The power dissipation and the related chip area, meanwhile, need to be low to generally reduce system power consumption and cost.
One conventional type of deserializer is a tree-type deserializer, where data delay elements such as registers or latches are allocated in a hierarchical structure, with some elements being operated at a significantly lower frequency than the source clock frequency. The tree deserializer has a significant advantage over register shift desrializers in its power consumption, but because the data is delivered among a variety of different clock domains, the data latency increases. Conventional tree deserializers are then unsuitable for applications that need low latency.